1. The host should support SDIO v2.0 with SDIO clock speeds of up to 50 MHz. Slower clock speeds will impact the maximum achievable throughput.
2. At a minimum, 2 x GPIOs are required as a CMOS output to drive the RESET and WAKE signals.  If power save is used, a third GPIO is needed, set as a CMOS input to receive the BUSY signal from the module.
3. The SDIO data and command lines should be pulled up with 10k-100k resistors as per the SDIO 2.0 specification.

When  selecting  a  CPU   host  to   interface  via  SPI  to  the  MM6108-MF08551  module,  consider  the  following recommendations to achieve the best throughput:

• The host should support level-triggered interrupts.
• The host should support full-duplex SPI mode.
• The host should support DMA backed transactions on the SPI bus.

All unused digital IO pins must be pulled up or down to ensure they do not float. Failure to do so will result in a higher leakage current on the VDDIO supply.